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MT9042C
Multitrunk System Synchronizer Advance Information
Features
* Meets jitter requirements for: AT&T TR62411 Stratum 3, 4 and Stratum 4 Enhanced for DS1 interfaces; and for ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 for E1 interfaces Provides C1.5, C3, C2, C4, C8 and C16 output clock signals Provides 8kHz ST-BUS framing signals Selectable 1.544MHz, 2.048MHz or 8kHz input reference signals Accepts reference inputs from two independent sources Provides bit error free reference switching meets phase slope and MTIE requirements Operates in either Normal, Holdover and Freerun modes
DS5144 ISSUE 2 September 1999
Ordering Information MT9042CP 28 Pin PLCC -40C to +85 C
* * * * * *
Description
The MT9042C Multitrunk System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9042C generates ST-BUS clock and framing signals that are phase locked to either a 2.048MHz, 1.544MHz, or 8kHz input reference. The MT9042C is compliant with AT&T TR62411 Stratum 3, 4 and 4 Enhanced, and ETSI ETS 300 011. It will meet the jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, holdover accuracy, capture range, phase slope and MTIE requirements for these specifications.
Applications
* * * Synchronization and timing control for multitrunk T1 and E1 systems ST-BUS clock and frame pulse sources Primary Trunk Rate Converters
TRST Virtual Reference DPLL
VDD
VSS
OSCi OSCo
Master Clock
TIE Corrector Circuit
Output Interface Circuit State Select Input Impairment Monitor Feedback Guard Time Circuit Frequency Select MUX
PRI SEC
Reference Select MUX Reference Select
Selected Reference TIE Corrector Enable
C1.5o C3o C2o C4o C8o C16o F0o F8o F16o
State Select
RSEL LOS1 LOS2
Automatic/Manual Control State Machine
MS1
MS2
RST
GTo
GTi
FS1
FS2
Figure 1 - Functional Block Diagram
1
MT9042C
Advance Information
VDD OSCo OSCi F16o F0o F8o C1.5o
4 3 2 1 28 27 26 5 25 24 6 7 23 22 8 21 9 20 10 19 11 12 13 14 15 16 17 18
TRST VSS RST FS1 FS2 RSEL MS1 MS2 LOS1 LOS2 GTo GTi
Figure 2 - Pin Connections
Pin Description
Pin # 1,15 2 Name VSS TRST Ground. 0 Volts. TIE Circuit Reset (TTL Input). A logic low at this input resets the Time Interval Error (TIE) correction circuit resulting in a re-alignment of input phase with output phase as shown in Figure 19. The TRST pin should be held low for a minimum of 300ns. Secondary Reference (TTL Input). This is one of two (PRI & SEC) input reference sources (falling edge) used for synchronization. One of three possible frequencies (8kHz, 1.544MHzMHz, or 2.048MHz) may be used. The selection of the input reference is based upon the MS1, MS2, LOS1, LOS2, RSEL, and GTi control inputs (Automatic or Manual). Primary Reference (TTL Input). See pin description for SEC. Positive Supply Voltage. +5VDC nominal. Oscillator Master Clock (CMOS Output). For crystal operation, a 20MHz crystal is connected from this pin to OSCi, see Figure 10. For clock oscillator operation, this pin is left unconnected, see Figure 9. Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal is connected from this pin to OSCo, see Figure 10. For clock oscillator operation, this pin is connected to a clock source, see Figure 9. Frame Pulse ST-BUS 16.384Mb/s (CMOS Output). This is an 8kHz 61ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 16.384Mb/s. See Figure 20. Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. See Figure 20. Frame Pulse ST-BUS 8.192Mb/s (CMOS Output). This is an 8kHz 122ns active high framing pulse, which marks the beginning of an ST-BUS frame. This is used for ST-BUS operation at 8.192Mb/s. See Figure 20. Clock 1.544MHz (CMOS Output). This output is used in T1 applications. Clock 3.088MHz (CMOS Output). This output is used in T1 applications. Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s. Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. Description (see notes 1 to 5)
3
SEC
4 5,18 6
PRI VDD OSCo
7
OSCi
8
F16o
9
F0o
10
F8o
11 12 13 14
C1.5o C3o C2o C4o
2
C3o C2o C4o VSS C8o C16o VDD
PRI SEC
Advance Information
Pin Description
Pin # 16 17 19 Name C8o C16o GTi Description (see notes 1 to 5)
MT9042C
Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s. Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation at 16.384Mb/ s. Guard Time (Schmitt Input). This input is used by the MT9042B state machine in both Manual and Automatic modes. The signal at this pin affects the state changes between Primary Holdover Mode and Primary Normal Mode, and Primary Holdover Mode and Secondary Normal Mode. The logic level at this input is gated in by the rising edge of F8o. See Tables 4 and 5. Guard Time (CMOS Output). The LOS1 input is gated by the rising edge of F8o, buffered and output on GTo. This pin is typically used to drive the GTi input through an RC circuit. Secondary Reference Loss (TTL Input). This input is normally connected to the loss of signal (LOS) output signal of a Line Interface Unit (LIU). When high, the SEC reference signal is lost or invalid. LOS2, along with the LOS1 and GTi inputs control the MT9042B state machine when operating in Automatic Control. The logic level at this input is gated in by the rising edge of F8o. Primary Reference Loss (TTL Input). Typically, external equipment applies a logic high to this input when the PRI reference signal is lost or invalid. The logic level at this input is gated in by the rising edge of F8o. See LOS2 description. Mode/Control Select 2 (TTL Input). This input, in conjunction with MS1, determines the device's mode (Automatic or Manual) and state (Normal, Holdover or Freerun) of operation. The logic level at this input is gated in by the rising edge of F8o. See Table 3. Mode/Control Select 1 (TTL Input). The logic level at this input is gated in by the rising edge of F8o. See pin description for MS1. Reference Source Select (TTL Input). In Manual Control, a logic low selects the PRI (primary) reference source as the input reference signal and a logic high selects the SEC (secondary) input. In Automatic Control, this pin must be at logic low. The logic level at this input is gated in by the rising edge of F8o. See Table 2. Frequency Select 2 (TTL Input). This input, in conjunction with FS1, selects which of three possible frequencies (8kHz, 1.544MHz, or 2.048MHz) may be input to the PRI and SEC inputs. See Table 1. Frequency Select 1 (TTL Input). See pin description for FS2. Reset (Schmitt Input). A logic low at this input resets the MT9042B. To ensure proper operation, the device must be reset after changes to the method of control, reference signal frequency changes and power-up. The RST pin should be held low for a minimum of 300ns. While the RST pin is low, all frame and clock outputs are at logic high. Following a reset, the input reference source and output clocks and frame pulses are phase aligned as shown in Figure 19.
20 21
GTo LOS2
22
LOS1
23
MS2
24 25
MS1 RSEL
26
FS2
27 28
FS1 RST
Notes: 1. All inputs are CMOS with either TTL compatible logic levels, CMOS compatible logic levels or Schmitt trigger compatible logic levels as indicated in the Pin Description. 2. All outputs are CMOS with CMOS compatible logic levels. 3. See DC Electrical Characteristics for static logic threshold values. 4. See AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels for dynamic logic threshold values. 5. Unless otherwise stated, all unused inputs should be connected to logic high or logic low and all unused outputs should be left open circuit.
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MT9042C
Functional Description
The MT9042C is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to interface circuits for T1 and E1 Primary Rate Digital Transmission links. Figure 1 is a functional block diagram which is described in the following sections. Reference Select MUX Circuit The MT9042C accepts two simultaneous reference input signals and operates on their falling edges. Either the primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Tables 1, 4 and 5. Frequency Select MUX Circuit The MT9042C operates with one of three possible input reference frequencies (8kHz, 1.544MHz or 2.048MHz). The frequency select inputs (FS1 and FS2) determine which of the three frequencies may be used at the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST) must be performed after every frequency select input change. Operation with FS1 and FS2 both at logic low is reserved and must not be used. See Table 1. FS2 0 0 1 1 FS1 0 1 0 1
Advance Information
Input Frequency Reserved 8kHz 1.544MHz 2.048MHz
Table 1 - Input Frequency Selection Time Interval Error (TIE) Corrector Circuit The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or SEC) from causing a step change in phase at the input of the DPLL block of Figure 1. During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary reference (SEC), a step change in phase on the output signals will occur. A phase step at the input of the DPLL will lead to unacceptable phase changes in the output signal. As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference. During a switch, from one reference to the other, the State Machine first changes the mode of the device
TRST Resets Delay Control Circuit Control Signal
Delay Value
PRI or SEC from Reference Select Mux
Programmable Delay Circuit
Virtual Reference to DPLL Compare Circuit
TIE Corrector Enable from State Machine
Feedback Signal from Frequency Select MUX
Figure 3 - TIE Corrector Circuit
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Advance Information
MT9042C
DPLL Reference to Output Interface Circuit
Virtual Reference from TIE Corrector
Phase Detector
Limiter
Loop Filter
Digitally Controlled Oscillator
Feedback Signal from Frequency Select MUX
State Select from Input Impairment Monitor
Control Circuit
State Select from State Machine
Figure 4 - DPLL Block Diagram from Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an accurate clock signal using storage techniques. The Compare Circuit then measures the phase delay between the current phase (feedback signal) and the phase of the new reference signal. This delay value is passed to the Programmable Delay Circuit (See Figure 3). The new virtual reference signal is now at the same phase position as the previous reference signal would have been if the reference switch not taken place. The State Machine then returns the device to Normal Mode. The DPLL now uses the new virtual reference signal, and since no phase step took place at the input of the DPLL, no phase step occurs at the output of the DPLL. In other words, reference switching will not create a phase change at the input of the DPLL, or at the output of the DPLL. Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL. This phase error is a function of the difference in phase between the two input reference signals during reference rearrangements. Each time a reference switch is made, the delay between input signal and output signal will change. The value of this delay is the accumulation of the error measured during each reference switch. The programmable delay circuit can be zeroed by applying a logic low pulse to the TIE Circuit Reset (TRST) pin. A minimum reset pulse width is 300ns. This results in a phase alignment between the input reference signal and the output signal as shown in Figure 20. The speed of the phase alignment correction is limited to 5ns per 125us, and convergence is in the direction of least phase travel. The state diagrams of Figure 7 and 8 indicate under which state changes the TIE Corrector Circuit is activated. Digital Phase Lock Loop (DPLL) As shown in Figure 4, the DPLL of the MT9042C consists of a Phase Detector, Limiter, Loop Filter, Digitally Controlled Oscillator, and a Control Circuit. Phase Detector - the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase difference between the two. This error signal is passed to the Limiter circuit. The Frequency Select MUX allows the proper feedback signal to be externally selected (e.g., 8kHz, 1.544MHz or 2.048MHz). Limiter - the Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all input transient conditions with a maximum output phase slope of 5ns per 125us. This is well within the maximum phase slope of 7.6ns per 125us or 81ns per 1.326ms specified by AT&T TR62411. Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all three reference frequency selections (8kHz, 1.544MHz or 2.048MHz). This filter ensures that the jitter transfer requirements in ETS 300 011 and AT&T TR62411 are met. Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input Impairment Circuit to set the mode of the DPLL. The three possible modes are Normal, Holdover and Freerun.
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MT9042C
Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop FIlter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the MT9042C. In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input reference signal. In Holdover Mode, the DCO is free running at a frequency equal to the last (less 30ms to 60ms) frequency the DCO was generating while in Normal Mode. In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20MHz source. Output Interface Circuit The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure 5. The Output Interface Circuit uses two Tapped Delay Lines followed by a T1 Divider Circuit and an E1 Divider Circuit to generate the required output signals.
Advance Information
The T1 Divider Circuit uses the 12.384MHz signal to generate two clock outputs. C1.5o and C3o are generated by dividing the internal C12 clock by four and eight respectively. These outputs have a nominal 50% duty cycle. The frame pulse outputs (F0o, F8o, F16o) are generated directly from the C16 clock. The T1 and E1 signals are generated from a common DPLL signal. Consequently, the clock outputs C1.5o, C3o, C2o, C4o, C8o, C16o, F0o and F16o are locked to one another for all operating states, and are also locked to the selected input reference in Normal Mode. See Figures 20 & 21. All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high capacitance (e.g., 30pF) loads. Input Impairment Monitor This circuit monitors the input signal to the DPLL and automatically enables the Holdover Mode (Auto-Holdover) when the frequency of the incoming signal is outside the auto-holdover capture range (See AC Electrical Characteristics - Performance). This includes a complete loss of incoming signal, or a large frequency shift in the incoming signal. When the incoming signal returns to normal, the DPLL is returned to Normal Mode with the output signal locked to the input signal. The holdover output signal is based on the incoming signal 30ms minimum to 60ms prior to entering the Holdover Mode. The amount of phase drift while in holdover is negligible because the Holdover Mode is very accurate (e.g., 0.05ppm). The the Auto-Holdover circuit does not use TIE correction. Consequently, the phase delay between the input and output after switching back to Normal Mode is preserved (is the same as just prior to the switch to Auto-Holdover). Automatic/Manual Control State Machine The Automatic/Manual Control State Machine allows the MT9042C to be controlled automatically (i.e., LOS1, LOS2 and GTi signals) or controlled manually (i.e., MS1, MS2, GTi and RSEL signals). With manual control a single mode of operation (i.e., Normal, Holdover and Freerun) is selected. Under automatic control the state of the LOS1, LOS2 and GTi signals determines the sequence of modes that the MT9042C will follow. As shown in Figure 1, this state machine controls the Reference Select MUX, the TIE Corrector Circuit, the
T1 Divider 12MHz Tapped Delay Line
C1.5o C3o
From DPLL
Tapped Delay Line
E1 Divider 16MHz
C2o C4o C8o C16o F0o F8o F16o
Figure 5 - Output Interface Circuit Block Diagram Two tapped delay lines are used to generate a 16.384MHz signal and a 12.352MHz signal. The E1 Divider Circuit uses the 16.384MHz signal to generate four clock outputs and three frame pulse outputs. The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively. These outputs have a nominal 50% duty cycle.
6
Advance Information
DPLL and the Guard Time Circuit. Control is based on the logic levels at the control inputs LOS1, LOS2, RSEL, MS1, MS2 and GTi of the Guard Time Circuit (See Figure 6).
To Reference Select MUX To TIE Corrector Enable To DPLL State Select
MT9042C
Control and Modes of Operation
The MT9042C can operate either in Manual or Automatic Control. Each control method has three possible modes of operation, Normal, Holdover and Freerun. As shown in Table 3, Mode/Control Select pins MS2 and MS1 select the mode and method of control. Control MANUAL RSEL 0 1 AUTO 0 Input Reference PRI SEC State Machine Control
RSEL LOS1 LOS2
Automatic/Manual Control State Machine
To and From Guard Time Circuit
MS1
MS2
Figure 6 - Automatic/Manual Control State Machine Block Diagram All state machine changes occur synchronously on the rising edge of F8o. See the Controls and Modes of Operation section for full details on Automatic Control and Manual Control. Guard Time Circuit The GTi pin is used by the Automatic/Manual Control State Machine in the MT9042C under either Manual or Automatic control. The logic level at the GTi pin performs two functions, it enables and disables the TIE Corrector Circuit (Manual and Automatic), and it selects which mode change takes place (Automatic only). See the Applications - Guard Time section. For both Manual and Automatic control, when switching from Primary Holdover to Primary Normal, the TIE Corrector Circuit is enabled when GTi=1, and disabled when GTi=0. Under Automatic control and in Primary Normal Mode, two state changes are possible (not counting Auto-Holdover). These are state changes to Primary Holdover or to Secondary Normal. The logic level at the GTi pin determines which state change occurs. When GTi=0, the state change is to Primary Holdover. When GTi=1, the state change is to Secondary Normal. Master Clock The MT9042C can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section.
1 Reserved Table 2 - Input Reference Selection
MS2 0 0 1 1
MS1 0 1 0 1
Control MANUAL MANUAL MANUAL AUTO
Mode NORMAL HOLDOVER FREERUN State Machine Control
Table 3 - Operating Modes and States Manual Control Manual Control should be used when either very simple MT9042C control is required, or when complex control is required which is not accommodated by Automatic Control. For example, very simple control could include operation in a system which only requires Normal Mode with reference switching using only a single input stimulus (RSEL). Very simple control would require no external circuitry. Complex control could include a system which requires state changes between Normal, Holdover and Freerun Modes based on numerous input stimuli. Complex control would require external circuitry, typically a microcontroller. Under Manual Control, one of the three modes is selected by mode/control select pins MS2 and MS1. The active reference input (PRI or SEC) is selected by the RSEL pin as shown in Table 2. Refer to Table 4 and Figure 7 for details of the state change sequences.
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MT9042C
Automatic Control Automatic Control should be used when simple MT9042C control is required, which is more complex than the very simple control provide by Manual Control with no external circuitry, but not as complex as Manual Control with a microcontroller. For example, simple control could include operation in a system which can be accommodated by the Automatic Control State Diagram shown in Figure 8. Automatic Control is also selected by mode/control pins MS2 and MS1. However, the mode and active reference source is selected automatically by the internal Automatic State Machine (See Figure 6). The mode and reference changes are based on the logic levels on the LOS1, LOS2 and GTi control pins. Refer to Table 5 and Figure 8 for details of the state change sequences. Normal Mode Normal Mode is typically used when a slave clock source, synchronized to the network is required. In Normal Mode, the MT9042C provides timing (C1.5o, C2o, C3o, C4o, C8o and C16o) and frame synchronization (F0o, F8o, F16o) signals, which are synchronized to one of two reference inputs (PRI or SEC). The input reference signal may have a nominal frequency of 8kHz, 1.544MHz or 2.048MHz. From a reset condition, the MT9042C will take up to 25 seconds for the output signal to be phase locked to the selected reference. The selection of input references is control dependent as shown in state tables 4 and 5. The reference frequencies are selected by the frequency control pins FS2 and FS1 as shown in Table 1. Holdover Mode Holdover Mode is typically used for short durations (e.g., 2 seconds) while network synchronization is temporarily disrupted. In Holdover Mode, the MT9042C provides timing and synchronization signals, which are not locked to an external reference signal, but are based on storage techniques. The storage value is determined while the device is in Normal Mode and locked to an external reference signal.
Advance Information
When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the MT9042C output frequency is stored alternately in two memory locations every 30ms. When the device is switched into Holdover Mode, the value in memory from between 30ms and 60ms is used to set the output frequency of the device. The frequency accuracy of Holdover Mode is 0.05ppm, which translates to a worst case 35 frame (125us) slips in 24 hours. This exceeds the AT&T TR62411 Stratum 3 requirement of 0.37ppm (255 frame slips per 24 hours). Two factors affect the accuracy of Holdover Mode. One is drift on the Master Clock while in Holdover Mode, drift on the Master Clock directly affects the Holdover Mode accuracy. Note that the absolute Master Clock (OSCi) accuracy does not affect Holdover accuracy, only the change in OSCi accuracy while in Holdover. For example, a 32ppm master clock may have a temperature coefficient of 0.1ppm per degree C. So a 10 degree change in temperature, while the MT9042C is in Holdover Mode may result in an additional offset (over the 0.05ppm) in frequency accuracy of 1ppm. Which is much greater than the 0.05ppm of the MT9042C. The other factor affecting accuracy is large jitter on the reference input prior (30ms to 60ms) to the mode switch. For instance, jitter of 7.5UI at 700Hz may reduce the Holdover Mode accuracy from 0.05ppm to 0.10ppm. Freerun Mode Freerun Mode is typically used when a master clock source is required, or immediately following system power-up before network synchronization is achieved. In Freerun Mode, the MT9042C provides timing synchronization signals which are based on master clock frequency (OSCi) only, and are synchronized to the reference signals (PRI SEC). and the not and
The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a 32ppm output clock is required, the master clock must also be 32ppm. See Applications - Crystal and Clock Oscillator sections.
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Advance Information
MT9042C
State Freerun GTi 0 1 X X X X S0 S1 S1 S2 / / Normal (PRI) S1 S2 MTIE S1H S2H S0 Normal (SEC) S2 S1 MTIE S1 MTIE / S2H S0 Holdover (PRI) S1H S1 S1 MTIE S2 MTIE / S0 Holdover (SEC) S2H S1 MTIE S1 MTIE S2 MTIE / S0
Description Input Controls MS2 0 0 0 0 0 1 MS1 0 0 0 1 1 0 RSEL 0 0 1 0 1 X
Legend: No Change / Not Valid MTIE State change occurs with TIE Corrector Circuit Refer to Manual Control State Diagram for state changes to and from Auto-Holdover State
Table 4 - Manual Control State Table
S0 Freerun (10X)
S1 Normal Primary (000)
{A}
S1A Auto-Holdover Primary (000)
S2A Auto-Holdover Secondary (001)
{A}
S2 Normal Secondary (001)
(GTi=0) (GTi=1)
S1H Holdover Primary (010)
S2H Holdover Secondary (011)
NOTES: (XXX) MS2 MS1 RSEL {A} Invalid Reference Signal Movement to Normal State from any state requires a valid input signal
Phase Re-Alignment Phase Continuity Maintained (without TIE Corrector Circuit) Phase Continuity Maintained (with TIE Corrector Circuit)
Figure 7 - Manual Control State Diagram
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MT9042C
Description Input Controls LOS2 1 X X 0 0 1 LOS1 1 0 0 1 1 1 GTi X 0 1 0 1 X RST 0 to 1 1 1 1 1 1 Freerun S0 S1 S1 S1 S2 Normal (PRI) S1 S0 S1H S2 MTIE S1H State Normal (SEC) S2 S0 S1 MTIE S1 MTIE S2H
Advance Information
Holdover (PRI) S1H S0 S1 S1 MTIE S2 MTIE -
Holdover (SEC) S2H S0 S1 MTIE S1 MTIE S2 MTIE S2 MTIE -
Legend: No Change MTIE State change occurs with TIE Corrector Circuit Refer to Automatic Control State Diagram for state changes to and from Auto-Holdover State
Table 5 - Automatic Control (MS1=MS2=1, RSEL=0) State Table
(11X) (11X) RST=1 Reset (X0X) S0 Freerun
(01X)
(X0X) (X0X) S1 Normal Primary (X0X) {A} S1A Auto-Holdover Primary
(01X) (01X) (01X) S2A Auto-Holdover Secondary {A} S2 Normal Secondary
(X0X) (011) (010 or 11X) (X00) (X01) S1H Holdover Primary S2H Holdover Secondary (11X) (X0X) (011) (01X)
(010 or 11X) NOTES: (XXX) LOS2 LOS1 GTi {A} Invalid Reference Signal Movement to Normal State from any state requires a valid input signal
(11X)
Phase Re-Alignment Phase Continuity Maintained (without TIE Corrector Circuit) Phase Continuity Maintained (with TIE Corrector Circuit)
Figure 8 - Automatic Control State Diagram
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Advance Information
MT9042C Measures of Performance
The following are some synchronizer performance indicators and their corresponding definitions. Intrinsic Jitter Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the output jitter of the device. Intrinsic jitter is usually measured with various bandlimiting filters depending on the applicable standards. Jitter Tolerance Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied jitter magnitude and jitter frequency depends on the applicable standards. Jitter Transfer Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. For the MT9042C, two internal elements determine the jitter attenuation. This includes the internal 1.9Hz low pass loop filter and the phase slope limiter. The phase slope limiter limits the output phase slope to 5ns/125us. Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited (i.e., attenuated) to 5ns/125us. The MT9042C has eight outputs with three possible input frequencies for a total of 24 possible jitter transfer functions. However, the data sheet section on AC Electrical Characteristics - Jitter Transfer specifies transfer values for only three cases, 8kHz to 8kHz, 1.544MHz to 1.544MHz and 2.048MHz to 2.048MHz. Since all outputs are derived from the same signal, these transfer values apply to all outputs.
MT9042C
It should be noted that 1UI at 1.544MHz is 644ns, which is not equal to 1UI at 2.048MHz, which is 488ns. Consequently, a transfer value using different input and output frequencies must be calculated in common units (e.g., seconds) as shown in the following example.
What is the T1 and E1 output jitter when the T1 input jitter is 20UI (T1 UI Units) and the T1 to T1 jitter attenuation is 18dB?
OutputT 1 = InputT 1 x10 OutputT 1 = 20 x10 - 18 ------- 20
- A ----- 20
= 2.5UI ( T 1 )
( 1UIT 1 ) OutputE1 = OutputT 1 x --------------------( 1UIE1 ) ( 644ns ) OutputE1 = OutputT 1 x ------------------- = 3.3UI ( T 1 ) ( 488ns )
Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on the three jitter transfer functions provided. Note that the resulting jitter transfer functions for all combinations of inputs (8kHz, 1.544MHz, 2.048MHz) and outputs (8kHz, 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz) for a given input signal (jitter frequency and jitter amplitude) are the same. Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance). Frequency Accuracy Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. For the MT9042C, the Freerun accuracy is equal to the Master Clock (OSCi) accuracy.
11
MT9042C
Holdover Accuracy Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the MT9042C, the storage value is determined while the device is in Normal Mode and locked to an external reference signal. The absolute Master Clock (OSCi) accuracy of the MT9042C does not affect Holdover accuracy, but the change in OSCi accuracy while in Holdover Mode does. Capture Range Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull into synchronization. The MT9042C capture range is equal to 230ppm minus the accuracy of the master clock (OSCi). For example, a 32ppm master clock results in a capture range of 198ppm. Lock Range This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock range is equal to the capture range for the MT9042C. Phase Slope Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. Time Interval Error (TIE) TIE is the time delay between a given timing signal and an ideal timing signal. Maximum Time Interval Error (MTIE) MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period. MTIE ( S ) = TIEmax ( t ) - TIEmin ( t ) Phase Continuity
Advance Information
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency. Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to a steady state. In the case of the MT9042C, the output signal phase continuity is maintained to within 5ns at the instance (over one frame) of all reference switches and all mode changes. The total phase shift, depending on the switch or type of mode change, may accumulate up to 200ns over many frames. The rate of change of the 200ns phase shift is limited to a maximum phase slope of approximately 5ns/125us. This meets the AT&T TR62411 maximum phase slope requirement of 7.6ns/125us (81ns/1.326ms). Phase Lock Time This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal and output signal are not changing in phase with respect to each other (not including jitter). Lock time is very difficult to determine because it is affected by many factors which include: i) initial input to output phase difference ii) initial input to output frequency difference iii) synchronizer loop filter iv) synchronizer limiter Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT9042C loop filter and limiter were optimized to meet the AT&T TR62411 jitter transfer and phase slope requirements. Consequently, phase lock time, which is not a standards requirement, may be longer than in other applications. See AC Electrical Characteristics Performance for maximum phase lock time.
12
Advance Information
MT9042C and Network Specifications
The MT9042C fully meets all applicable PLL requirements (intrinsic jitter, jitter tolerance, jitter transfer, frequency accuracy, holdover accuracy, capture range, phase change slope and MTIE during reference rearrangement) for the following specifications. 1. AT&T TR62411 (DS1) December 1990 for Stratum 3, Stratum 4 Enhanced and Stratum 4 2. ANSI T1.101 (DS1) February 1994 for Stratum 3, Stratum 4 Enhanced and Stratum 4 3. ETSI 300 011 (E1) April 1992 for Single Access and Multi Access 4. TBR 4 November 1995 5. TBR 12 December 1993 6. TBR 13 January 1996 7. ITU-T I.431 March 1993
MT9042C
Applications
This section contains MT9042C application specific details for clock and crystal operation, guard time usage, reset operation, power supply decoupling, Manual Control operation and Automatic Control operation. Master Clock The MT9042C can use either a clock or crystal as the master timing source. In Freerun Mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source at the OSCi pin. For applications not requiring an accurate Freerun Mode, tolerance of the master timing source may be 100ppm. For applications requiring an accurate Freerun Mode, such as AT&T TR62411, the tolerance of the master timing source must Be no greater than 32ppm. Another consideration in determining the accuracy of the master timing source is the desired capture range. The sum of the accuracy of the master timing source and the capture range of the MT9042C will always equal 230ppm. For example, if the master timing source is 100ppm, then the capture range will be 130ppm. Clock Oscillator - when selecting a Clock Oscillator, numerous parameters must be considered. This includes absolute frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle. See AC Electrical Characteristics.
MT9042C OSCi +5V
+5V 20MHz OUT GND 0.1uF
OSCo No Connection
Figure 9 - Clock Oscillator Circuit For applications requiring 32ppm clock accuracy, the following clock oscillator module may be used.
13
MT9042C
CTS CXO-65-HG-5-C-20.0MHz Frequency: 20MHz Tolerance: 25ppm 0C to 70C Rise & Fall Time: 8ns (0.5V 4.5V 50pF) Duty Cycle: 45% to 55%
Advance Information
Load Capacitance: 32pF Maximum Series Resistance: 35 Approximate Drive Level: 1mW e.g., CTS R1027-2BB-20.0MHZ (20ppm absolute, 6ppm 0C to 50C, 32pF, 25)
The output clock should be connected directly (not AC coupled) to the OSCi input of the MT9042C, and the OSCo output should be left open as shown in Figure 9. Crystal Oscillator - Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made up of a crystal, resistor and capacitors is shown in Figure 10.
MT9042C OSCi 20MHz 1M
Guard Time Adjustment AT&T TR62411 recommends that excessive switching of the timing reference should be minimized. And that switching between references only be performed when the primary signal is degraded (e.g., error bursts of 2.5 seconds). Minimizing switching (from PRI to SEC) in the MT9042C can be realized by first entering Holdover Mode for a predetermined maximum time (i.e., guard time). If the degraded signal returns to normal before the expiry of the guard time (e.g., 2.5 seconds), then the MT9042C is returned to its Normal Mode (with no reference switch taking place). Otherwise, the reference input may be changed from Primary to Secondary.
MT9042C
56pF OSCo 100
39pF
3-50pF
1uH
GTo R 150k
1uH inductor: may improve stability and is optional
Figure 10 - Crystal Oscillator Circuit The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. Typically, for a 20MHz crystal specified with a 32pF load capacitance, each 1pF change in load capacitance contributes approximately 9ppm to the frequency deviation. Consequently, capacitor tolerances, and stray capacitances have a major effect on the accuracy of the oscillator frequency. The trimmer capacitor shown in Figure 10 may be used to compensate for capacitive effects. If accuracy is not a concern, then the trimmer may be removed, the 39pF capacitor may be increased to 56pF, and a wider tolerance crystal may be substituted. The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. The crystal specification is as follows.
Frequency: Tolerance: Oscillation Mode: Resonance Mode:
14
+
C 10uF
GTi RP 1k
Figure 11 - Symmetrical Guard Time Circuit A simple way to control the guard time (using Automatic Control) is with an RC circuit as shown in Figure 11. Resistor RP is for protection only and limits the current flowing into the GTi pin during power down conditions. The guard time can be calculated as follows. V DD guard time = RC x ln --------------------------------- V DD - V SIH guard time RC x 0.6 example guard time 150k x 10u x 0.6 = 0.9s
* VSIH is the logic high going threshold level for the GTi Schmitt Trigger input, see DC Electrical Characteristics
20MHz As required Fundamental Parallel
Advance Information
MT9042C
SEC SIGNAL STATUS LOS2 PRI SIGNAL STATUS
GOOD
GOOD
BAD TD
GOOD TD
BAD
GOOD
LOS1
GTo VSIH GTi
MT9042C STATE
PRI NORMAL
PRI HOLDOVER
PRI NORMAL
PRI HOLDOVER
SEC NORMAL
PRI NORMAL
NOTES: 1. TD represents the time delay from when the reference goes bad to when the MT9042C is provided with a LOS indication.
Figure 12 - Automatic Control, Unsymmetrical Guard Time Circuit Timing Example In cases where fast toggling might be expected of the LOS1 input, then an unsymmetrical Guard Time Circuit is recommended. This ensures that reference switching doesn't occur until the full guard time value has expired. An unsymmetrical Guard Time Circuit is shown in Figure 12.
MT9042C GTo RC 150k
TIE Correction (using GTi) When Primary Holdover Mode is entered for short time periods, TIE correction should not be enabled. This will prevent unwanted accumulated phase change between the input and output. This is mainly applicable to Manual Control, since Automatic Control together with the Guard Time Circuit inherently operate in this manner. For instance, 10 Normal to Holdover to Normal mode change sequences occur, and in each case Holdover was entered for 2s. Each mode change sequence could account for a phase change as large as 350ns. Thus, the accumulated phase change could be as large as 3.5us, and, the overall MTIE could be as large as 3.5us. Phase hold = 0.05 ppm x 2s = 100ns Phase state = 50ns + 200ns = 250ns Phase 10 = 10 x ( 250ns + 100ns ) = 3.5us
* * * 0.05ppm is the accuracy of Holdover Mode 50ns is the maximum phase continuity of the MT9042C from Normal Mode to Holdover Mode 200ns is the maximum phase continuity of the MT9042C from Holdover Mode to Normal Mode (with or without TIE Corrector Circuit)
+
RD 1k GTi RP 1k
C 10uF
Figure 13 - Unsymmetrical Guard Time Circuit Figure 13 shows a typical timing example of an unsymmetrical Guard Time Circuit with the MT9042C in Automatic Control.
15
MT9042C
Advance Information
To Line 1
MT9074 TTIP DSTo DSTi
To TX Line XFMR
TRING F0i C4i MT9042C E1.5o LOS PRI SEC + 5V MT9074 TTIP DSTo DSTi 1k F0i C4i LOS1 LOS2 MS1 MS2 RSEL TRST RST 10k 10nF CLOCK Out 20MHz 32ppm OSCi + 5V 10uF E1.5o LOS 1k + FS1 FS2 150k GTo GTi 1k F0o C4o C2o + 5V
RTIP To RX Line XFMR RRING
To Line 2
To TX Line XFMR
TRING
RTIP To RX Line XFMR RRING
MT8985 STo0 STi0 STo1 STi1 F0i C4i
Figure 14 - Dual T1 Reference Sources with MT9042C in 1.544MHz Automatic Control
When 10 Normal to Holdover to Normal mode change sequences occur without MTIE enabled, and in each case holdover was entered for 2s, each mode change sequence could still account for a phase change as large as 350ns. However, there would be no accumulated phase change, since the input to output phase is re-aligned after every Holdover to Normal state change. The overall MTIE would only be 350ns. Reset Circuit A simple power up reset circuit with about a 50us reset low time is shown in Figure 15. Resistor RP is for protection only and limits current into the RST pin during power down conditions. The reset low time is not critical but should be greater than 300ns.
16
MT9042C +5V R 10k RST RP 1k C 10nF
Figure 15 - Power-Up Reset Circuit
Advance Information
MT9042C
To Line 1 To TX Line XFMR
MT9075 TTIP TRING F0i C4i RxFP LOS MT9042C PRI SEC F0o C4o + 5V DSTo DSTi
RTIP To RX Line XFMR RRING
To Line 2
MT9075 TTIP DSTo DSTi
To TX Line XFMR
LOS1 C1.5o LOS2 FS1 MS1 FS2 MS2 RSEL GTi TRST RST OSCi
TRING RTIP F0i C4i RxFP LOS
CLOCK Out 20MHz 32ppm
To RX Line XFMR
RRING
External Stimulus CONTROLLER MT8985 STo0 STi0 STo1 STi1 F0i C4i
Figure 16 - Dual E1 Reference Sources with MT9042C in 8kHz Manual Control
Power Supply Decoupling The MT9042C has two VDD (+5V) pins and two VSS (GND) pins. Power and decoupling capacitors should be included as shown in Figure 17.
C1 0.1uF
+
18
15 MT9042C
1 C2 0.1uF
5
Figure 17 - Power Supply Decoupling
+
17
MT9042C
Absolute Maximum Ratings* Parameter 1 2 3 4 5 Supply voltage Voltage on any pin Current on any pin Storage temperature PLCC package power dissipation
Advance Information
Voltages are with respect to ground (V SS) unless otherwise stated.
Symbol VDD VPIN IPIN TST PPD
Min -0.3 -0.3
Max 7.0 VDD+0.3 20
Units V V mA C mW
-55
125 900
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions* - * Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 Supply voltage Operating temperature Sym VDD TA Min 4.5 -40 Max 5.5 85 Units V C
DC Electrical Characteristics* - * Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 5 6 7 8 9 10 11 Supply current with: OSCi = 0V OSCi = Clock TTL high-level input voltage TTL low-level input voltage CMOS high-level input voltage CMOS low-level input voltage Schmitt high-level input voltage Schmitt low-level input voltage Schmitt hysteresis voltage Input leakage current High-level output voltage Sym IDDS IDD VIH VIL VCIH VCIL VSIH VSIL VHYS IIL VOH 0.4 -10 0.8VDD +10 2.3 0.8 0.7VDD 0.3VDD 2.0 0.8 Min Max 10 60 Units mA mA V V V V V V V uA V V OSCi OSCi GTi, RST GTi, RST GTi, RST VI=VDD or 0V IOH=4mA IOL=4mA Conditions/Notes Outputs unloaded Outputs unloaded
12 Low-level output voltage VOL 0.2VDD * Supply voltage and operating temperature are as per Recommended Operating Conditions.
18
Advance Information
AC Electrical Characteristics - Performance
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Phase lock time Output phase continuity with: reference switch Capture range with OSCi at: Holdover Mode accuracy with OSCi at: Freerun Mode accuracy with OSCi at: 0ppm 32ppm 100ppm 0ppm 32ppm 100ppm 0ppm 32ppm 100ppm Sym Min -0 -32 -100 -0.05 -0.05 -0.05 -230 -198 -130 Max +0 +32 +100 +0.05 +0.05 +0.05 +230 +198 +130 30 200 200 200 50 600 45 8kHz -18k -36k -36k +18k +36k +36k Units ppm ppm ppm ppm ppm ppm ppm ppm ppm s ns ns ns ns ns us/s ppm ppm ppm
MT9042C
Conditions/Notes 5-8 5-8 5-8 1,2,4,6-8,40 1,2,4,6-8,40 1,2,4,6-8,40 1-3,6-8 1-3,6-8 1-3,6-8 1-3,6-14 1-3,6-14 1-2,4-14 1-,4,6-14 1-3,6-14 1-14,27 1-14,27 1-3,6,9-11 1-3,7,9-11 1-3,8-11
mode switch to Normal mode switch to Freerun mode switch to Holdover MTIE (maximum time interval error) Output phase slope Reference input for Auto-Holdover with:
1.544MHz 2.048MHz
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels* - Voltages are
with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 Threshold Voltage Rise and Fall Threshold Voltage High Rise and Fall Threshold Voltage Low
Sym VT VHM VLM
Schmitt 1.5 2.3 0.8
TTL 1.5 2.0 0.8
CMOS 0.5VDD 0.7VDD 0.3VDD
Units V V V
* Supply voltage and operating temperature are as per Recommended Operating Conditions. * Timing for input and output signals is based on the worst case result of the combination of TTL and CMOS thresholds. * See Figure 18.
Timing Reference Points ALL SIGNALS tIRF, tORF tIRF, tORF V HM VT VLM
Figure 18 - Timing Parameter Measurement Voltage Levels
19
MT9042C
AC Electrical Characteristics - Input/Output Timing
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Reference input pulse width high or low Reference input rise or fall time 8kHz reference input to F8o delay 1.544MHz reference input to F8o delay 2.048MHz reference input to F8o delay F8o to F0o delay F16o setup to C16o falling F16o hold from C16o rising F8o to C1.5o delay F8o to C3o delay F8o to C2o delay F8o to C4o delay F8o to C8o delay F8o to C16o delay C1.5o pulse width high or low C3o pulse width high or low C2o pulse width high or low C4o pulse width high or low C8o pulse width high or low C16o pulse width high or low F0o pulse width low F8o pulse width high F16o pulse width low Output clock and frame pulse rise or fall time Input Controls Setup Time Input Controls Hold Time Sym tRW tIRF tR8D tR15D tR2D tF0D tF16S tF16H tC15D tC3D tC2D tC4D tC8D tC16D tC15W tC3W tC2W tC4W tC8W tC16WL tF0WL tF8WH tF16WL tORF tS tH
Advance Information
Min 100
Max
Units ns
10 -21 337 222 110 11 0 -51 -51 -13 -13 -13 -13 309 149 230 111 52 24 230 111 52 6 363 238 134 35 20 -37 -37 2 2 2 2 339 175 258 133 70 35 258 133 70 9 100 100
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
See "Notes" following AC Electrical Characteristics tables.
20
Advance Information
MT9042C
tR8D
PRI/SEC 8kHz tR15D PRI/SEC 1.544MHz tR2D PRI/SEC 2.048MHz
tRW tRW
VT
VT tRW VT
F8o NOTES: 1. Input to output delay values are valid after a TRST or RST with no further state changes
VT
Figure 19 - Input to Output Timing (Normal Mode)
tF8WH F8o tF0WL F0o tF16WL F16o tF16S tC16WL C16o tC8W C8o tC4W C4o tC2W C2o tC3W C3o tC15W C1.5o tC15D VT tC3W tC3D VT tC2D VT tC4W tC4D VT tC8W tC8D VT tF16H VT tF0D VT VT
tC16D
VT
Figure 20 - Output Timing 1
21
MT9042C
Advance Information
F8o tS MS1,2 LOS1,2 RSEL, GTi tH
VT
VT
Figure 21 - Input Controls Setup and Hold Timing
AC Electrical Characteristics - Intrinsic Jitter Unfiltered
Characteristics 1 2 3 4 5 6 7 8 9 Intrinsic jitter at F8o (8kHz) Intrinsic jitter at F0o (8kHz) Intrinsic jitter at F16o (8kHz) Intrinsic jitter at C1.5o (1.544MHz) Intrinsic jitter at C2o (2.048MHz) Intrinsic jitter at C3o (3.088MHz) Intrinsic jitter at C4o (4.096MHz) Intrinsic jitter at C8o (8.192MHz) Intrinsic jitter at C16o (16.384MHz) Sym Min Max 0.0002 0.0002 0.0002 0.030 0.040 0.060 0.080 0.160 0.320 Units UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp Conditions/Notes 1-14,21-24,28 1-14,21-24,28 1-14,21-24,28 1-14,21-24,29 1-14,21-24,30 1-14,21-24,31 1-14,21-24,32 1-14,21-24,33 1-14,21-24,34
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - C1.5o (1.544MHz) Intrinsic Jitter Filtered
Characteristics 1 2 3 4 Intrinsic jitter (4Hz to 100kHz filter) Intrinsic jitter (10Hz to 40kHz filter) Intrinsic jitter (8kHz to 40kHz filter) Intrinsic jitter (10Hz to 8kHz filter) Sym Min Max 0.015 0.010 0.010 0.005 Units UIpp UIpp UIpp UIpp Conditions/Notes 1-14,21-24,29 1-14,21-24,29 1-14,21-24,29 1-14,21-24,29
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - C2o (2.048MHz) Intrinsic Jitter Filtered
Characteristics 1 2 3 4 Intrinsic jitter (4Hz to 100kHz filter) Intrinsic jitter (10Hz to 40kHz filter) Intrinsic jitter (8kHz to 40kHz filter) Intrinsic jitter (10Hz to 8kHz filter) Sym Min Max 0.015 0.010 0.010 0.005 Units UIpp UIpp UIpp UIpp Conditions/Notes 1-14,21-24,30 1-14,21-24,30 1-14,21-24,30 1-14,21-24,30
See "Notes" following AC Electrical Characteristics tables
22
Advance Information
AC Electrical Characteristics - 8kHz Input to 8kHz Output Jitter Transfer
Characteristics 1 2 3 4 5 6 Jitter attenuation for 1Hz@0.01UIpp input Jitter attenuation for 1Hz@0.54UIpp input Jitter attenuation for 10Hz@0.10UIpp input Jitter attenuation for 60Hz@0.10UIpp input Jitter attenuation for 300Hz@0.10UIpp input Jitter attenuation for 3600Hz@0.005UIpp input Sym Min 0 6 12 28 42 45 Max 6 16 22 38 Units dB dB dB dB dB dB
MT9042C
Conditions/Notes 1-3,6,9-14,21-22,24,28,35 1-3,6,9-14,21-22,24,28,35 1-3,6,9-14,21-22,24,28,35 1-3,6,9-14,21-22,24,28,35 1-3,6,9-14,21-22,24,28,35 1-3,6,9-14,21-22,24,28,35
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - 1.544MHz Input to 1.544MHz Output Jitter Transfer
Characteristics 1 2 3 4 5 6 7 Jitter attenuation for 1Hz@20UIpp input Jitter attenuation for 1Hz@104UIpp input Jitter attenuation for 10Hz@20UIpp input Jitter attenuation for 60Hz@20UIpp input Jitter attenuation for 300Hz@20UIpp input Jitter attenuation for 10kHz@0.3UIpp input Jitter attenuation for 100kHz@0.3UIpp input Sym Min 0 6 12 28 42 45 45 Max 6 16 22 38 Units dB dB dB dB dB dB dB Conditions/Notes 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - 2.048MHz Input to 2.048 MHz Output Jitter Transfer
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Jitter at output for 1Hz@3.00UIpp input with 40Hz to 100kHz filter Jitter at output for 3Hz@2.33UIpp input with 40Hz to 100kHz filter Jitter at output for 5Hz@2.07UIpp input with 40Hz to 100kHz filter Jitter at output for 10Hz@1.76UIpp input with 40Hz to 100kHz filter Jitter at output for 100Hz@1.50UIpp input with 40Hz to 100kHz filter Jitter at output for 2400Hz@1.50UIpp input with 40Hz to 100kHz filter Jitter at output for 100kHz@0.20UIpp input with 40Hz to 100kHz filter Sym Min Max 2.9 0.09 1.3 0.10 0.80 0.10 0.40 0.10 0.06 0.05 0.04 0.03 0.04 0.02 Units UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp Conditions/Notes 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36
See "Notes" following AC Electrical Characteristics tables. 23
MT9042C
AC Electrical Characteristics - 8kHz Input Jitter Tolerance
Characteristics 1 2 3 4 5 6 7 8 Jitter tolerance for 1Hz input Jitter tolerance for 5Hz input Jitter tolerance for 20Hz input Jitter tolerance for 300Hz input Jitter tolerance for 400Hz input Jitter tolerance for 700Hz input Jitter tolerance for 2400Hz input Jitter tolerance for 3600Hz input Sym Min 0.80 0.70 0.60 0.20 0.15 0.08 0.02 0.01 Max Units UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
Advance Information
Conditions/Notes 1-3,6,9-14,21-22,24-26,28 1-3,6,9-14,21-22,24-26,28 1-3,6,9-14,21-22,24-26,28 1-3,6,9-14,21-22,24-26,28 1-3,6,9-14,21-22,24-26,28 1-3,6,9-14,21-22,24-26,28 1-3,6,9-14,21-22,24-26,28 1-3,6,9-14,21-22,24-26,28
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - 1.544MHz Input Jitter Tolerance
Characteristics 1 2 3 4 5 6 7 8 9 Jitter tolerance for 1Hz input Jitter tolerance for 5Hz input Jitter tolerance for 20Hz input Jitter tolerance for 300Hz input Jitter tolerance for 400Hz input Jitter tolerance for 700Hz input Jitter tolerance for 2400Hz input Jitter tolerance for 10kHz input Jitter tolerance for 100kHz input Sym Min 150 140 130 35 25 15 4 1 0.5 Max Units UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp Conditions/Notes 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - 2.048MHz Input Jitter Tolerance
Characteristics 1 2 3 4 5 6 7 8 9 Jitter tolerance for 1Hz input Jitter tolerance for 5Hz input Jitter tolerance for 20Hz input Jitter tolerance for 300Hz input Jitter tolerance for 400Hz input Jitter tolerance for 700Hz input Jitter tolerance for 2400Hz input Jitter tolerance for 10kHz input Jitter tolerance for 100kHz input Sym Min 150 140 130 50 40 20 5 1 1 Max Units UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp Conditions/Notes 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30
See "Notes" following AC Electrical Characteristics tables.
24
Advance Information
AC Electrical Characteristics - OSCi 20MHz Master Clock Input
Characteristics 1 2 3 4 5 6 Duty cycle Rise time Fall time Frequency accuracy (20 MHz nominal) Sym Min -0 -32 -100 40 Max +0 +32 +100 60 10 10 Units ppm ppm ppm % ns ns
MT9042C
Conditions/Notes 15,18 16,19 17,20
See "Notes" following AC Electrical Characteristics tables.
Notes:
Voltages are with respect to ground (VSS) unless otherwise stated. Supply voltage and operating temperature are as per Recommended Operating Conditions. Timing parameters are as per AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels 1. PRI reference input selected. 2. SEC reference input selected. 3. Normal Mode selected. 4. Holdover Mode selected. 5. Freerun Mode selected. 6. 8kHz Frequency Mode selected. 7. 1.544MHz Frequency Mode selected. 8. 2.048MHz Frequency Mode selected. 9. Master clock input OSCi at 20MHz 0ppm. 10. Master clock input OSCi at 20MHz 32ppm. 11. Master clock input OSCi at 20MHz 100ppm. 12. Selected reference input at 0ppm. 13. Selected reference input at 32ppm. 14. Selected reference input at 100ppm. 15. For Freerun Mode of 0ppm. 16. For Freerun Mode of 32ppm. 17. For Freerun Mode of 100ppm. 18. For capture range of 230ppm. 19. For capture range of 198ppm. 20. For capture range of 130ppm. 21. 25pF capacitive load. 22. OSCi Master Clock jitter is less than 2nspp, or 0.04UIpp where1UIpp=1/20MHz. 23. Jitter on reference input is less than 7nspp. 24. Applied jitter is sinusoidal. 25. Minimum applied input jitter magnitude to regain synchronization. 26. Loss of synchronization is obtained at slightly higher input jitter amplitudes. 27. Within 10ms of the state, reference or input change. 28. 1UIpp = 125us for 8kHz signals. 29. 1UIpp = 648ns for 1.544MHz signals. 30. 1UIpp = 488ns for 2.048MHz signals. 31. 1UIpp = 323ns for 3.088MHz signals. 32. 1UIpp = 244ns for 4.096MHz signals. 33. 1UIpp = 122ns for 8.192MHz signals. 34. 1UIpp = 61ns for 16.384MHz signals. 35. No filter. 36. 40Hz to 100kHz bandpass filter. 37. With respect to reference input signal frequency. 38. After a RST or TRST. 39. Master clock duty cycle 40% to 60%. 40. Prior to Holdover Mode, device was in Normal Mode and phase locked.
25
MT9042C
Advance Information
F
A G
D1 D
D2
H E E1 e: (lead coplanarity) A1 I E2 Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) For D & E add for allowable Mold Protrusion 0.010"
20-Pin
Dim
28-Pin Min
0.165 (4.20) 0.090 (2.29) 0.485 (12.32)
44-Pin Min
0.165 (4.20) 0.090 (2.29) 0.685 (17.40)
68-Pin Min
0.165 (4.20) 0.090 (2.29) 0.985 (25.02)
84-Pin Min
0.165 (4.20) 0.090 (2.29) 1.185 (30.10)
Min
A A1 D/E D1/E1 D2/E2 e F G H I
0.165 (4.20) 0.090 (2.29) 0.385 (9.78) 0.350 (8.890) 0.290 (7.37) 0 0.026 (0.661) 0.013 (0.331)
Max
0.180 (4.57) 0.120 (3.04) 0.395 (10.03)
Max
0.180 (4.57) 0.120 (3.04) 0.495 (12.57)
Max
0.180 (4.57) 0.120 (3.04) 0.695 (17.65)
Max
0.200 (5.08) 0.130 (3.30) 0.995 (25.27)
Max
0.200 (5.08) 0.130 (3.30) 1.195 (30.35)
0.356 0.450 0.456 0.650 0.656 0.950 0.958 1.150 1.158 (9.042) (11.430) (11.582) (16.510) (16.662) (24.130) (24.333) (29.210) (29.413) 0.330 (8.38) 0.004 0.032 (0.812) 0.021 (0.533) 0.390 (9.91) 0 0.026 (0.661) 0.013 (0.331) 0.430 (10.92) 0.004 0.032 (0.812) 0.021 (0.533) 0.590 (14.99) 0 0.026 (0.661) 0.013 (0.331) 0.630 (16.00) 0.004 0.032 (0.812) 0.021 (0.533) 0.890 (22.61) 0 0.026 (0.661) 0.013 (0.331) 0.930 (23.62) 0.004 0.032 (0.812) 0.021 (0.533) 1.090 (27.69) 0 0.026 (0.661) 0.013 (0.331) 1.130 (28.70) 0.004 0.032 (0.812) 0.021 (0.533)
0.050 BSC (1.27 BSC) 0.020 (0.51)
0.050 BSC (1.27 BSC) 0.020 (0.51)
0.050 BSC (1.27 BSC) 0.020 (0.51)
0.050 BSC (1.27 BSC) 0.020 (0.51)
0.050 BSC (1.27 BSC) 0.020 (0.51)
Plastic J-Lead Chip Carrier - P-Suffix
26
Advance Information
Notes:
MT9042C
27
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